期刊名称：International Journal of Soft Computing & Engineering
电子版ISSN：2231-2307
出版年度：2015
卷号：4
期号：6
页码：54-63
出版社：International Journal of Soft Computing & Engineering
摘要：Here it is explained how can be designed by an easy form, and using HDL tool, a thread for implement the algorithm for natural binary format to decimal (BCD) format. In order to achieve that, here is released an explanation of such algorithm in a fast and needed way. In VHDL, structural style will be used for build each one modules for the Arithmetic Unit as well as those modules for Control Unit. The program is the set of instructions. Each instruction is a single operation as a sum, a shift, a comparison and so on. Every those instructions are carried out by a single module in VHDL. The memory to store the program it is implement by array of registers. That array is executed in a sequence by which is driven by a Program Counter (PC). The complete architecture it is explain step by step in order to it can be used as application note or a tutorial, and repeated by teachers, students and hobbyist. The complete processor it is builds in a single CPLD from Lattice Semiconductor. That is the ispMACH LC4256ZE 5TN144C device
关键词：Binary natural to decimal BCD format; tutorial on;how design a thread
