期刊名称：International Journal of Soft Computing & Engineering
电子版ISSN：2231-2307
出版年度：2015
卷号：5
期号：4
页码：103-106
出版社：International Journal of Soft Computing & Engineering
摘要：In this paper we propose a new concept for multiplication by using modified booth algorithm, booth multiplier & wellece tree multiplier and reversible logic function. By combining modified booth algorithm with reversible gate logic it will produces further less delay compare to all other. Addition subtraction operation are realized using reversible DKG gate. Reversible logic circuits have theoretically zero internal power dissipation because they do not lose information, the classical set of gates such as AND, OR, and XOR are not reversible. This modified booth multiplier, modified booth multiplier & wellece tree multiplier with reversible gate logic are synthesized and simulated by using Xilinx 13.2 ISE simulator
