期刊名称：International Journal of Innovative Research in Computer and Communication Engineering
印刷版ISSN：2320-9798
电子版ISSN：2320-9801
出版年度：2013
卷号：1
期号：4
出版社：S&S Publications
摘要：Due to increased complexity of SoC designs, the importance of design reuse, verification, and debuggingincreased. Theoretically these concepts seem simple and easy to implement, but there are number of challenges thatdesign and verification team must address while practical implementation. For example, one of the significant barriersto IP reuse is the wide variety of design languages used in IP design and verification. Some of the commonly usedlanguages for design and verification are SystemVerilog, SystemC and conventional HDL languages such as Verilogand VHDL. These languages have their unique strengths which make them more suitable for writing certain portions ofa design or IP. But for design to be successful, all of its individual components must communicate with each otherwhich are in the different languages. This paper provides guidelines and ways of how to communicate withSystemVerilog and SystemC. It describes different approaches and provides useful insights to help users to integratesIP blocks in a SystemVerilog environment.
