期刊名称：International Journal of Innovative Research in Computer and Communication Engineering
印刷版ISSN：2320-9798
电子版ISSN：2320-9801
出版年度：2013
卷号：1
期号：8
出版社：S&S Publications
摘要：This article emphasized on FPGA design to develop AES CORE using verilog HDL. Mainly the workfocus on 5 modules like, key generation, shift rows, mix columns, xoring module and top module- integration. All thesemodules are authorized in verilog HDL language. The key generation module generates required keys from the givenkey. The left circular shift operation is performed by shift rows. The mix columns perform the matrix multiplicationwith constant matrix. Xoring module specifies the xoring the text data with the key. The top module indicates theintegration of all modules and it is treated as the AES Core. Prior to AES, Data Encryption Standard (DES) is a widelyused method of data encryption using a private (secret) key that was so difficult to break. With the Triple DESimplementation of DES, there are 5.1 * 1033 or more possible encryption keys that can be used.
