期刊名称：International Journal of Innovative Research in Computer and Communication Engineering
印刷版ISSN：2320-9798
电子版ISSN：2320-9801
出版年度：2014
卷号：2
期号：4
出版社：S&S Publications
摘要：Digital down converter (DDC) is very important and integral part of the multi - rate wireless communication s ystem. As it utilize s the major resources, therefore its low cost and efficient implementation is of main concern. This paper presents and implements a FPGA based optimized design of decimation filter for wireless commun ication recei vers. Cascaded integrated comb (C IC) filters are multiplier less linear filters which are extensively used in multi - rate systems for the purpose of di gital down conversion (DDC). An optimized architecture based upon these filters is analyzed a nd implemented. The prototype of the proposed filter is designed to decimate the input signal having sampling rate 10 MHz, by the decimation factor of 8 using Matlab - Simulink Model and Xilinx System Generator. The design is implemented on Vertex - 5 based xc 5vlx110t - 3 - ff1136 target device. The proposed design consumed considerably less resources on the target device to provide an efficient design for multi - rate wireless communication receivers.
关键词：Digital filters; DDC; digital down converter; CIC; de ; cimation filter; multi ; rate communication system; decimator; cascaded integrated comb; Non ; - ; recursive filter; Matlab Simulink; Xilinx System Generator
