期刊名称：International Journal of Hybrid Information Technology
印刷版ISSN：1738-9968
出版年度：2015
卷号：8
期号：10
页码：405-416
DOI：10.14257/ijhit.2015.8.10.37
出版社：SERSC
摘要：Design based upon CMOS logic are becoming increasingly attractive for many applications under electronic gadgets, but with increasing demand of small and portable devices, new techniques for low power are emerging. This paper focus on the design of subtarction logic for ALU sub-module in microprocessor design. Set of four different 10-T subtraction logic using Gate Diffusion Index(a new technique for low power design) has been designed using 180nm technology using Cadence Virtuoso and simulation are performed . Complete verification for performance of proposed subtraction logic is carried and circuit with least power and delay has been selected for the ALU design of the microprocessor. Layout design for the best optimum ciruit is designed using Layout XL and area of 17.28 X 11.135 m 2 is calculated.
关键词：ALU; CMOS; Delay; Full Subtractor; GDI; Low power design
