期刊名称：International Journal of Signal Processing, Image Processing and Pattern Recognition
印刷版ISSN：2005-4254
出版年度：2014
卷号：7
期号：4
页码：57-64
DOI：10.14257/ijsip.2014.7.4.05
出版社：SERSC
摘要：Nowadays, for providing the secure facilities and services to the user, the accurate identification is necessary. The Iris recognition is one of the attractive approach for user's identification, provides high level of security and convenience then the other methods of identification like traditional ID and password, which can be lost or transferred. However, the iris recognition algorithms are implemented on general purpose sequential processing systems, such as generic central processing units (CPUs). Parallel processing is an alternative offers an opportunity to enhance the performance of system by increasing the speed. The most time consuming part of Iris recognition algorithm is matching part, which is implemented using Verilog HDL through ISE Design suit (14.2), achieved significantly reduction in execution time. The proposed design is suitable for integration either in ASIC or FPGA.
