期刊名称：International Journal of Signal Processing, Image Processing and Pattern Recognition
印刷版ISSN：2005-4254
出版年度：2015
卷号：8
期号：5
页码：75-86
DOI：10.14257/ijsip.2015.8.5.08
出版社：SERSC
摘要：The design of phase frequency detector (PFD) using CMOS current mode logic (CML_PFD) is presented in this paper. Further its performance has been compared with a proposed PFD, denoted here as M_CML_PFD. The simulation results are focused on accounting the power dissipation, delay and output noise. Both the PFDs are designed to be dead zone free and using 0.35μm CMOS technology on SPICE simulator. The output noise experienced is reduced by 6.5% in M_CML_PFD. The power dissipation of the proposed M_CML_PFD is 15.72% lesser and delay is 2.37 times less than the CML_PFD when operating at 100 MHz input frequency with 3.3V voltage supply
关键词：Phase Locked Loop; High Speed Integrated Circuits; Phase frequency ; detector; Current Mode Logic; D flip flop
