期刊名称：International Journal of Signal Processing, Image Processing and Pattern Recognition
印刷版ISSN：2005-4254
出版年度：2015
卷号：8
期号：9
页码：167-174
DOI：10.14257/ijsip.2015.8.9.17
出版社：SERSC
摘要：A 4th-Order low-distortion low-pass ΣΔ modulator structure is proposed in this paper, which uses the timing-sharing between the 3rd and 4th integrators during one clock phase. Compared with conventional cascade of integrators with distributed feed-forward (CIFF) sigma-delta modulator structure, the proposed structure not only solves the critical timing issue for the quantizer and feedback DAC path, but also eliminates an extra active adder to sum up the input feed-forward. By methods of delay redistribution structure, the time for quantization and feedback dynamic element match (DEM) operation can be extended from a non-overlapping interval for a conventional low- distortion structure to half of the sampling clock period. Capacitive input feed-forward (CIF) methodology eliminates the adder in front of the quantizer. Further, the op-amp of the last integrator is used as an active adder by op-amp sharing. Therefore, the power consumption can be reduced and the linearity of the feedback DAC is improved because of the increasing time which used for implementation of DEM algorism. The proposed 4th-Order low-distortion low-pass ΣΔ modulator with 4-bit quantizer is simulated in MATLAB. From the simulation results, the proposed structure can achieve a peak SNR (signal-to-noise ratio) of 87dB with 2.5MHz bandwidth under 32 oversampling ratio at 160MHz sampling frequency and the ENOB of 14.234bits in non-ideal condition
关键词：low-distortion; low-pass; time-sharing; sigma-delta; differential sampling; ; dynamic element match
