摘要：This paper throws light on the behavior of the UART in response to the variations in the junction temperature. Analysis has been done to find the most ideal temperature range for the operation of the UART. After all the calculations, deduction comes to a point that lowering the temperature values increases the efficiency of the UART significantly since the losses due to the leakage power are reduced to a minimum value when the temperature is decreased. Significant reduction in the percentage of leakage power is seen as the temperature is lowered. Implementation has been done on the FPGA generations Virtex-6, Virtex-5, Virtex-4 using XILINX simulator and Verilog Hardware Description Language. Different reduction percentages have been observed within a range of 8% to 37.4% for the leakage power and 16.8% to 69.3%for the ambient temperature as the results are obtained for frequency values of 1GHz and 1MHz. Thus various power loss parameters have been studied to get the best energy efficient UART.
关键词：FPGA; Energy Efficient; Universal Asynchronous Receiver Transmitter; ; Thermal Scaling
