期刊名称：International Journal of Electronics Communication and Computer Engineering
印刷版ISSN：2249-071X
电子版ISSN：2278-4209
出版年度：2011
卷号：2
期号：1
页码：27-29
出版社：IJECCE
摘要：This paper targets the implementation of a MIPS (Microprocessor without Interlocked Pipeline Stages) RISC (Reduced Instruction Set Computer) Processor via VHDL (Very high speed integrated circuit Hardware Description Language) design. The goal of this paper is to enhance the simulator based approach by integrating some hardware design {&} simulating them in pipelined (3 level) {&} non-pipelined modes so as to assess the performance of the processor in each of the modes
