期刊名称：International Journal of Electronics Communication and Computer Engineering
印刷版ISSN：2249-071X
电子版ISSN：2278-4209
出版年度：2011
卷号：2
期号：2
页码：151-154
出版社：IJECCE
摘要：The aim of this paper is to design and verify the physical layer implementation by using ISE 8.1 from Xilinx and Spartan 3 FPGA to reduce the cost and hardware as well without affecting the performance and reliability of PCI Express. PCI is the third generation high performance I/O bus used to interconnect peripheral devices in applications such as computing and communicating platform. PCI Express is an all in compassing I/O device interconnect bus that has application in the Mobile, Desktop, Workstation, Server, Embedded computing and communication platform. PCS is the sub layer of the physical layer of PCI Express 1.0. The major constituents of this layer are transmitter and receiver. Transmitter comprises of 8b/10b encoder. The Primary purpose of this scheme is to embed a clock into the serial bit stream of transmitter lanes with advancement in the design by reducing the utilized hardware resources within FPGA. No clock is transmitted along with the serial data bit stream. This eliminates EMI noise and provides DC balance. Receiver comprises of special symbol detector, elastic buffer and 8b/10b decoder. . 8b/10b decoder gives 8bit character and data/control signals. Disparity error and Decode error can be known though this module. If any error is present in the received data then loopback signal is generated. This work uses VHDL to model different blocks of the PCS of physical layer of PCI Express. The RTL code is simulated, synthesized and implemented using the ISE 8.1 from Xilinx and the Spartan 3 FPGA was targeted for implementation. In this paper we have reduced the hardware as well as cost of total system without affecting the speed of the PCI Express
关键词：EMI Noise Electromagnetic interference also called radio frequency interference or RFI; FPGA Field- Programmable Gate Array; PCI-SIG Peripheral Component Interconnect Special Interest Group; VHDL Very High Speed IC Hardware description Language
