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  • 标题:Parametric Analysis of 4-Bit Adder/Subtractor.
  • 本地全文:下载
  • 作者:Nimade, P. S. ; Gupta, P. V ; Shukla, A
  • 期刊名称:International Journal of Electronics Communication and Computer Engineering
  • 印刷版ISSN:2249-071X
  • 电子版ISSN:2278-4209
  • 出版年度:2012
  • 卷号:3
  • 期号:5
  • 页码:1199-1202
  • 出版社:IJECCE
  • 摘要:Adders are key components in digital design, performing not only addition operations, but also many other functions such as subtraction, multiplication and division. Adders of various bit widths are frequently required in Very Large-Scale Integrated circuits (VLSI) from processors to Application Specific Integrated Circuits (ASICs).This paper deals with layout of 4-bit full adder/subtractor. It can be use as a adder circuit for 4bit addition and also as a subtractor for subtraction with a clock signal. The result of simulation of adder/subtractor layout is in Microwind2.
  • 关键词:Full Adder; Subtractor; Tox; phi; VLSI; Microwind2
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