期刊名称：International Journal of Electronics Communication and Computer Engineering
印刷版ISSN：2249-071X
电子版ISSN：2278-4209
出版年度：2012
卷号：3
期号：5
页码：1286-1289
出版社：IJECCE
摘要：Symmetric Transparent BIST has been proposed as a means to skip the signature prediction phase during RAM testing thereby testing time can be reduced. The proposed symmetric transparent BIST scheme is for single bit and multiple bit (word) RAM’s. The principle of this is a characteristic of a polynomial is modified based on the application of sequence of March events. In this paper an FSM is used to generate the mach events and are applied for the RAM to verify it. Compared to previous BIST techniques, controller complexity is reduced. Due to the reduction in the controller complexity the hardware required for the BIST also reduces and thereby reducing the power and delay.
关键词：Built in self test; design for testability; integrated circuit reliability; Self testing; RAM testing
