期刊名称：International Journal of Electronics Communication and Computer Engineering
印刷版ISSN：2249-071X
电子版ISSN：2278-4209
出版年度：2012
卷号：3
期号：6
页码：1580-1585
出版社：IJECCE
摘要：The primary objective of this work was to implement an innovative architecture that computes the basic Data Encryption Standard (DES), which is used in a wide range of communication systems to protect information being transmitted over a channel from being intercepted and read by unauthorized parties. DES is probably one of the best known cryptographic algorithms, and has been widely used. Compared to software implementations, hardware implementations of the DES algorithm provide more physical security as well as higher speed. As compared to the existing DES implementations in the present design, this work targets at a higher operating frequency, higher throughput by enhancing on the lines of pipelining concept. The pipelined structure minimizes the computation time overhead by key and message loading. The DES mode of operation is considered is the basic Electronic Code Book (ECB). Further the utility of scan chains is used as a side channel attack to recover the secret key from the hardware implementation of the DES. Scan chains are used to discover the secret key stored in the cryptographic devices. The round keys are recovered using certain mathematical assumptions, on the scanned out bits. The hardware architecture is described using Verilog HDL and is simulated to test its functionality.
关键词：Data Encryption Algorithm; Electronic Code Book; Side Channel Attack
