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文章基本信息

  • 标题:Area Efficient Single Phase Clock Divider
  • 本地全文:下载
  • 作者:Nandhakumar, R. ; Jagadeeshwaran, C ; Sundhari, R. P
  • 期刊名称:International Journal of Electronics Communication and Computer Engineering
  • 印刷版ISSN:2249-071X
  • 电子版ISSN:2278-4209
  • 出版年度:2013
  • 卷号:4
  • 期号:1
  • 页码:298-302
  • 出版社:IJECCE
  • 摘要:In this paper the prescaler circuit which is used by frequency synthesizers of Bluetooth, zigbee and WLAN is proposed with multi modulus 32/33/47/48 prescaler, ultra low power 2/3 prescaler and integrated P-counter and S-counter. This proposed prescaler can divide the frequency in three bands 0f 2.4-2.484GHz, 5.15-5.35GHz and 5.725-5.825GHz with a resolution selectable from 1-25MHz.The Area and power consumed by the 2/3 prescaler circuit is minimized
  • 关键词:DFF; Frequency Synthesizer; U-TSPC; Wireless LAN WLAN; True Single Phase Clock TSPC
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