期刊名称：International Journal of Electronics Communication and Computer Engineering
印刷版ISSN：2249-071X
电子版ISSN：2278-4209
出版年度：2013
卷号：4
期号：1
页码：7-11
出版社：IJECCE
摘要：In this paper I had implemented the different three types of 4-bit adder using adiabatic logic and conventional CMOS logic in 45nm technology with LT spice. As we know Full adders are important components in applications such as digital signal processors (DSP) architectures and microprocessors. Apart from the basic addition adders also used in performing useful operations such as subtraction, multiplication, division, address calculation, etc. we have compared all three techniques conventional CMOS, 1n-1p Quasi and 1n-1p split level logic in 1-bit as well as 4-bit adder for power dissipation and as result suggest adiabatic method has low power dissipation compared to conventional CMOS. We got minimum power dissipation and energy consumption in 1n-1p split adiabatic logic
