期刊名称：International Journal of Electronics Communication and Computer Engineering
印刷版ISSN：2249-071X
电子版ISSN：2278-4209
出版年度：2013
卷号：4
期号：2
页码：422-426
出版社：IJECCE
摘要：A CMOS based low power 4-bit Flash Analog to Digital Converter (ADC) design with reduced number of comparators than the conventional Flash Analog to Digital Converter and multiplexer based architecture is proposed. For improving the conversion rate, both the analog and digital parts of the ADC are fully modified and the architecture uses only 4 comparators instead of 15 as used in conventional flash ADC, thus saving considerable amount of power. The proposed 4-bit ADC is designed and simulated in TANNER tools with 1.2 V supply voltage using TSpice simulation. The proposed design consumes low power of 2.15mW and operates at a faster rate hence it is suitable for ECG applications
