期刊名称：International Journal of Electronics Communication and Computer Engineering
印刷版ISSN：2249-071X
电子版ISSN：2278-4209
出版年度：2014
卷号：5
期号：2
页码：426-430
出版社：IJECCE
摘要：Error control is the major insistence in today’s wireless communication systems. In this era parallel concatenated convolutional codes known as turbo codes plays a crucial role. These codes have been chosen as error control approach for various wireless applications such as UMTS (Universal Mobile Telecommunication System),DVB (Digital Video Broadcasting) etc. In this paper an area efficient turbo encoder (2, 1, 3) is proposed to suffice the elevated demand of miniaturization in future wireless communication. The proposed design is simulated using matlab and synthesized on Xilinx Virtex-2p (xc2vp30-ff896-5) FPGA. During simulation the proposed design is compared with the matlab model of RSC encoder. The performance of proposed Turbo encoder will be compared for FPGAs in terms of number of slices, number of slice Flip-flops and the number of registers. The Synthesis results show a 7% improvement in the utilized no. of slices and slice flip-flop. So an area efficient, cost effective Parallel Concatenated Convolutional Code Encoder has been proposed in this paper
