期刊名称：International Journal of Engineering and Computer Science
印刷版ISSN：2319-7242
出版年度：2013
卷号：2
期号：3
页码：588-592
出版社：IJECS
摘要：A design of 16 bit processor is programmed in VHDL. The processor module is added with extra hardware logic calle d Trojan.A fault bit pattern is injected into the circuit along with the processor clock. The fault bit patterns triggers the extra hardware hidden in the processor that can be detected by verifying the output result from memory and CPU
