期刊名称：International Journal of Engineering and Computer Science
印刷版ISSN：2319-7242
出版年度：2013
卷号：2
期号：6
页码：2037-2040
出版社：IJECS
摘要：As the technology improving, the system-on-chip designs become more and more complex. For the verification of these complex SoC designs, coverage metrics and the responses to them guide the entire verification flow. As like the designs are moving towards reusable and portable environments, the verification components and verification environments should also supports reusability. Hence there is a need for standalone, pre-verified and built-in verification infrastructure, which can be easily plugged in the verification environment. The Verification Intellectual Property (Verification IP) is an integral and important component of such infrastructure, which aids designers and verification engineers in the task of validating the functionality of their design. The developed Verification IP, in this paper provides the ability to verify a design against the requirements of a standard AMBA AXI4-Lite protocol. It includes the functional coverage models to track back the verification progress. This verification IP will help engineers to quickly create verification environment and test their AXI4-Lite master and slave devices
