期刊名称：International Journal of Engineering and Computer Science
印刷版ISSN：2319-7242
出版年度：2013
卷号：2
期号：10
页码：2895-2899
出版社：IJECS
摘要：Power is arguably the critical resource in VLSI system design today. In this paper a brief review is discussed aboutdrowsy cache & also about the “Variation Trained Drowsy Cache” (VTD-Cache) architecture. As process technology scalesdown, leakage power consumption becomes comparable to dynamic power consumption. The drowsy cache technique isknown as one of the most popular techniques for reducing the leakage power consumption in the data cache. However, thedrowsy cache is reported to degrade the processor performance significantly. In this paper VTD-Cache allows for a significantreduction of around 50% in power consumption while addressing reliability issues raised by memory cell process variability.By managing voltage scaling at a very fine granularity, each cache way can be sourced at a different voltage where theselection of voltage levels depends on both the vulnerability of the memory cells in that cache way to process variation and thelikelihood of access to that cache location. The novel and modular architecture of the VTD-Cache and its associated controllermakes it easy to be implemented in memory compilers with a small area and power overhead. This total process is studied withdifferent diagrams ,schematics using Xilinx 14.5 software
