期刊名称：International Journal of Engineering and Computer Science
印刷版ISSN：2319-7242
出版年度：2014
卷号：3
期号：3
页码：5004-5007
出版社：IJECS
摘要：A new CMOS voltage-mode Four-quadrant analog Multiplier is proposed and analyzed by applying inputs signals to set ofSummation circuit and substractor. Based on the proposed multiplier circuit, a low voltage high performance CMOS four quadrantanalog multiplier is designed and simulated by using 0.35 micron technology. The measured 3dB bandwidth is 15 MHz. Simplestructure, low-voltage, low power, and high performance makes the proposed multiplier quite feasible in many applications
