期刊名称：International Journal of Engineering and Computer Science
印刷版ISSN：2319-7242
出版年度：2014
卷号：3
期号：11
页码：9343-9346
出版社：IJECS
摘要：the most timing critical part of logic design usually contains one or more arithmetic operations, in which addition iscommonly involved. Addition is a fundamental arithmetic operation and it is the base for arithmetic operations such asmultiplication and the basic adder cell can be modified to function as subtractor by adding another XOR gate. Therefore, 1-bit FullAdder cell is the most important and basic block of an arithmetic unit of a system. Hence in order to improve the performance ofthe digital computer system one must improve the basic 1-bit full adder cell based application. In this paper simulate theperformance of 4 bit adder- subtractor, 4 bit Carry skip adder and 4-bit multipliers are designed using 9T full adder. All thesimulation results are using TSMC-0.18μM CMOS Technology
关键词：full adder; Power consumption; Adder;Subtractor; Multiplication
