期刊名称：International Journal of Engineering and Computer Science
印刷版ISSN：2319-7242
出版年度：2014
卷号：3
期号：12
页码：9598-9601
出版社：IJECS
摘要：Multiplier is an important key element used for arithmetic operations in digital signal processor. Power consumption inmultiplier is more when compared with adders and subtractors. So reducing the power consumption of multiplier makes a digital signalprocessor more efficient. A Wallace tree multiplier is an efficient high speed multiplier that multiplies two integers. Here a 4*4 Wallace treemultiplier is proposed with ten full adders. Each full adder used in this design has only nine transistor which is less in number whencompared with the conventional full adders. Due to this the power consumption of full adder block is reduced, such that power consumptionof 4*4 Wallace Tree Multiplier will be reduced. The proposed design is simulated using 0.12μm technology in Microwind 2 Tool and hasachieved upto 50% power saving in comparison to the Wallace Tree Multiplier that has been designed using Conventional Full adder
关键词：Full adder; Multiplier; Wallace Tree Multiplier; Power consumption
