期刊名称：International Journal of Engineering and Computer Science
印刷版ISSN：2319-7242
出版年度：2014
卷号：3
期号：12
页码：9761-9765
出版社：IJECS
摘要：Cyclic Redundancy Check is playing a vital role in the networking environment to detect the errors. With challenging speed oftransmitting data and to synchronize with speed, it’s necessary to increase speed of CRC generation. This paper presents 64 bits parallelCRC architecture based on F-matrix with order of generator polynomial is 32. Implemented design is hardware efficient and requires 50%less cycles to generate CRC with same order of generator polynomial. CRC32 bit is used in Ethernet frame for error detection. The wholedesign is functionally developed and verified using Xilinx ISE 12.3i Simulator
关键词：Cyclic Redundancy Check(CRC); Parallel CRC calculation; Linear Feedback Shift Register (LFSR); F matrix
