期刊名称：International Journal of Engineering and Computer Science
印刷版ISSN：2319-7242
出版年度：2015
卷号：4
期号：1
页码：9994-9998
出版社：IJECS
摘要：In today’s modern system-on-chips , there are several intellectual properties on the system to provide different functionality.However, more complex communications on SoCs the harder at which the programmer could discover all errors before firstsilicon during its verification. Therefore, it provides a reconfigurable unit for recording the transactions between IPs and adoptlogical vector clock as a time stamp of each trace. The programmable trigger unit in debugging node could be configured by thevalidation to cache their interest sequences of transaction. Because traces of transactions would have their own timestamp, duringthe post-silicon validation, finally it could reproduce the errors in faulty transactions between IPs and get more information for bypassing or fixing the problems. In future, due to several entries of traces finally shrink observation window very quickly, it alsoimplement a compressor to compress traces before it store them into trace buffer. Finally,experiments demonstrate that theproposed debugging architecture is capable of recording the critical transactions, and the proposed reconfigurable debugging unitwhole debugging execution time can be reduced more than 80%.
