期刊名称：International Journal of Engineering and Computer Science
印刷版ISSN：2319-7242
出版年度：2015
卷号：4
期号：5
页码：11825-11829
出版社：IJECS
摘要：Full Adder is the basic building block for various arithmetic circuits such as compressors, multipliers, comparators and soon. 1-bit Full Adder cell is the important and basic block of an arithmetic unit of a system. Hence in order to improve the performanceof the digital computer system one must improve the basic 1-bit full adder cell. In this, Full Adder is designed by using Hybrid-CMOSlogic style. Hybrid designs are used to build a low power Full Adder cell. In the hybrid logic style more than one network is present. Ingeneral, it consists of three modules. Here we proposed the new Full Adder design by using the GDI (Gate Diffusion Index/Input)technique.GDI is a new method for reducing the power consumption, propagation delay, with less transistor count and power delayproduct (PDP).The simulation results are carried out on Tanner EDA tool. The simulation shows that the design has more efficient withless area, less power consumption and high speed as compared to CMOS techniques
关键词：GDI technique; Low power; Full Adder; High speed
