期刊名称：International Journal of Engineering and Computer Science
印刷版ISSN：2319-7242
出版年度：2015
卷号：4
期号：5
页码：11830-11834
出版社：IJECS
摘要：Low Power VLSI is the major area in VLSI design to develop the product in smart way. High performance isthe keystone of the designer’s idea. Performance depends upon the speed, reduce-in-delay, less power consumption andmajorly cost. In low power VLSI design, the contribution of adder is another platform. Design of an adder is to be moreefficient and at the same time the internal parameters such as area, power, delay, cost to be monitor. Along with thebenefits of super-fast performance the reduction of delay is a big advantage of using these types of adders. On the otherhand, the formations of different inputs and to process those inputs are the difficult to implement. To overcome thosedifficulties, BEC based CSA are used. To process a complexity mathematical inputs like squaring of inputs some specialcircuit are to be use. Such a special circuit is the SQRT and along with CSLA it is called as SQRT-CSLA. Discussion istaken place how to implement the SQRT-CSLA to analysis the practical values. ASIC, SOC implementation is mostpopular in this type of implementation. In an existing methodology, it was analysed that the synthesis by ASIC resultsBEC-based SQRT-CSLA design involves 48% more ADP and consumes 50% more energy than the proposed SQRTCSLA,on average, for different bit-widths. We are focusing on this point, how to maximize the efficiency by utilize thepower less and maximum result in the output. Also, in an existing system the implementation is going with 64 bit widthsas maximum and this clearly describes the factor how increase of the product efficiency took place. But in our proposedmethodology, we are going to adopt the processing bits of the range 128 bits.
关键词：Carry Select Adder; Binary to Excess Code;Area-Delay-Product
