期刊名称：International Journal of Engineering and Computer Science
印刷版ISSN：2319-7242
出版年度：2015
卷号：4
期号：5
页码：11835-11839
出版社：IJECS
摘要：In digital circuits Clock signal is one of the factor causing dynamic power consumption.Clock Gating is a method applied forreducing the dynamic power dissipation in sequential circuits.Here the redundant clock pulses in a high frequency clock signal areeliminated by performing AND operation on Enable signal and applied clock signal.Enable signal is determined by performing XORoperation on input and output of sequential element such as Flipflop.ANDed output—the Gated clock signal serves as clock to theexisting circuit, which consists of clock pulses at the switching activities of input signal.This method can be extended to group ofFlipflops having similarly switching inputs by performing OR operation on the enable signals of all Flipflops in the group.When thisgroup drives a combinational circuit the leakage power exists,when the circuit is in stand-by mode i.e no existence of pulse in Gatedclock signal.For eliminating this,we are introducing Power gating in which Gated clock signal is given as a sleep signal to NMOStransistor in pull down section.The simulation results are carried out on Tanner EDA tool.The simulation shows that the design hasmore efficient with less power consumption in CMOS techniques.
