期刊名称：International Journal of Engineering and Computer Science
印刷版ISSN：2319-7242
出版年度：2015
卷号：4
期号：6
页码：12499-12507
出版社：IJECS
摘要：Memory cores are usually the densest portion with the smallest feature size in system-on-chip (SOC) designs. Thereliability of memory cores thus has heavy impact on the reliability of SOCs. Transparent test is one of useful technique forimproving the reliability of memories during life time. Transparent BIST schemes for RAM modules assure the preservation ofthe memory contents during periodic testing Symmetric Transparent Built-in Self Test (BIST) schemes skip the signatureprediction phase required in traditional transparent BIST. Achieving considerable reduction in test time. Previous works orsymmetric transparent BIST schemes require that a separate BIST module is utilized for each RAM under test. This approach,giver the large number of memories available in current chips, increase the hardware overhead of the BIST circuitry. In thiswork we propose a Symmetric transparent BIST scheme that can be utilized to test Rams. For 5 different word widths hence,more than one RAMs can be tested in a roving manner
