期刊名称：International Journal of Engineering and Computer Science
印刷版ISSN：2319-7242
出版年度：2015
卷号：4
期号：7
页码：13101-13105
出版社：IJECS
摘要：Digital multipliers are among the most critical arithmetic functional units. The overall performance of theDigital multiplier systems depends on throughput of the multiplier. The negative bias temperature instability effect occurswhen a pMOS transistor is under negative bias (Vgs = −Vdd), increasing the threshold voltage of a pMOS transistor andreducing the multiplier speed. Similarly, positive bias temperature instability occurs when an nMOS transistor is underpositive bias. Both effects degrade the speed of the transistor and in the long term, the system may be fail due to timingviolations. Therefore, it is required to design reliable high-performance multipliers. In this paper, we implement an agingawaremultiplier design with a novel adaptive hold logic (AHL) circuit. The multiplier is able to provide the higherthroughput through the variable latency and can adjust the adaptive hold logic (AHL) circuit to lessen performancedegradation that is due to the aging effect. The proposed design can be applied to the column bypass multiplier
关键词：Adaptive hold logic (AHL); negative bias temperature instability (NBTI); positive bias temperature;instability(PBTI); reliable multiplier; variable latency
