期刊名称：International Journal of Engineering and Computer Science
印刷版ISSN：2319-7242
出版年度：2015
卷号：4
期号：7
页码：13585-13600
出版社：IJECS
摘要：Clock gating is one among the most widespread circuit technique to scale back power consumption.Clock gating is sometimes done at the register transfer level (RTL). Automatic synthesis of clock gating in gate levelhas been less explored, however it's certainly additional convenient to designers.Clock gating consists of 2 steps:extraction of gating conditions by merging gating conditions of individual flip-flops, implementation of the gatingconditions with minimum quantity of further gates.In this paper,We show a way to do factored form matching,within which gating operates in factored kinds ar matched, as way as possible, with factored kinds of themathematician functions of existing combinable nodes within the circuit; further gates are then introduced,however just for the portion of gating functions that don't seem to be matched. sturdy matching identifiesmatches that ar explicitly gift within the factored forms, and weak matching seeks matches that ar inexplicit thelogic and so are tougher to get
