期刊名称：International Journal of Engineering and Computer Science
印刷版ISSN：2319-7242
出版年度：2015
卷号：4
期号：10
页码：14589-14593
DOI：10.18535/ijecs/v4i10.9
出版社：IJECS
摘要：This paper proposes new processor architecture for accelerating data-parallel applications based on thecombination of VLIW and vector processing paradigms. It uses VLIW architecture for processing multiple independentscalar instructions concurrently on parallel execution units. Data parallelism is expressed by vector ISA and processed onthe same parallel execution units of the VLIW architecture. The proposed processor, which is called VecLIW, has unifiedregister file of 64x32-bit registers in the decode stage for storing scalar/vector data. VecLIW can issue up to fourscalar/vector operations in each cycle for parallel processing a set of operands and producing up to four results. However,it cannot issue more than one memory operation at a time, which loads/stores 128-bit scalar/vector data from/to datacache. Four 32-bit results can be written back into VecLIW register file. The complete design of our proposed VecLIWprocessor is implemented using Verilog HDL
