期刊名称：International Journal of Engineering and Computer Science
印刷版ISSN：2319-7242
出版年度：2015
卷号：4
期号：10
页码：14670-14676
DOI：10.18535/ijecs/v4i10.22
出版社：IJECS
摘要：Although tremendous progress has done in past years on memory designing but still Radiation-induced soft errors is concernedarea in the field of soft memories and the single error correction double error detection (SEC-DED) codes are commonly used togive assured memory contents with absence of corrupted scenario. Since SEC-DED codes cannot correct multiple errors, they areoften combined with interleaving. Interleaving, however, impacts memory design and performance and cannot always be used insmall memories. This limitation has spurred interest in codes that can correct adjacent bit errors. In particular, several SEC-DEDdouble adjacent error correction (SEC-DED-DAEC) codes have recently been proposed. Implementing DAEC has a cost as itimpacts the decoder complexity and delay. Another issue is that most of the new SEC-DED-DAEC codes miscorrect some doublenonadjacent bit errors. In this brief, a new class of SEC-DED-DAEC codes is derived from orthogonal Latin squares codes. Thenew codes significantly reduce the decoding complexity and delay. In addition, the codes do not miscorrect any double nonadjacentbit errors. The main disadvantage of the new codes is that they require a larger number of parity check bits. Therefore, they can beuseful when decoding delay or complexity is critical or when miscorrection of double nonadjacent bit errors is not acceptable. Theproposed codes have been implemented in Hardware Description Language and compared with some of the existing SEC-DEDDAECcodes. Finally the experimental results confirm the reduction in decoder delay.
关键词：Error correction codes; Orthogonal Latin square codes. Single error correction double error detection (SEC-DED);Double adjacent error correction (DAEC); Memory
