期刊名称：International Journal of Engineering and Computer Science
印刷版ISSN：2319-7242
出版年度：2016
卷号：5
期号：1
页码：15487-15491
DOI：10.18535/Ijecs/v5i1.15
出版社：IJECS
摘要：In this paper proposed power and area efficient discrete cosine transform (DCT) architecture formultimedia applications. This paper Implemented conventional DCT and multiplier less DCT‟s by lessnumber of adders/subtracter and multipliers. Area and power achieved by reducing mathematical operations.Number of cells, cell area, internal power, net power, leakage power, switching power reduced compared toconventional DCT. Power delay product of both conventional DCT and multiplier less DCT‟s are 19.8mJ,19.7mJ and 10.8 mJ respectively. The proposed DCT and conventional DCT are implemented on cadenceRTL compiler 180nm
