摘要：Resistive switching through electroresistance (ER) effect in metal-ferroelectric-metal (MFM) capacitors has attracted increasing interest due to its potential applications as memories and logic devices. However, the detailed electronic mechanisms resulting in large ER when polarisation switching occurs in the ferroelectric barrier are still not well understood. Here, ER effect up to 1000% at room temperature is demonstrated in C-MOS compatible MFM nanocapacitors with a 8.8 nm-thick poly(vinylidene fluoride) (PVDF) homopolymer ferroelectric, which is very promising for silicon industry integration. Most remarkably, using theory developed for metal-semiconductor rectifying contacts, we derive an analytical expression for the variation of interfacial barrier heights due to space-charge effect that can interpret the observed ER response. We extend this space-charge model, related to the release of trapped charges by defects, to MFM structures made of ferroelectric oxides. This space-charge model provides a simple and straightforward tool to understand recent unusual reports. Finally, this work suggests that defect-engineering could be an original and efficient route for tuning the space-charge effect and thus the ER performances in future electronic devices.
