期刊名称：International Journal of Innovative Research in Computer and Communication Engineering
印刷版ISSN：2320-9798
电子版ISSN：2320-9801
出版年度：2014
卷号：2
期号：10
出版社：S&S Publications
摘要：Vedic mathematics is an ancient system of mathematics which performs unique technique ofcalculations based on 16 sutras. The performance of high speed multiplier is designed based on Urdhva Tiryabhyam,Nikhilam Navatashcaramam Dashatah, and Anurupye algorithms. These algorithms gives minimum delay and used formultiplication of all types of numbers. The performance of high speed multiplier is designed and compared using thesesutras for various NxN bit multiplications and implemented on the FFT of the DSP processor. Anurupye Vedicmultiplier on FFT is made efficient than Urdhva tiryabhyam and Nikhilam Navatashcaramam Dashatah sutras by morereduction in computation time. Logic verification of these design is verified by simulating the logic circuits in XILINXISE 9.1 and MODELSIM SE 5.7g using VHDL.
