期刊名称：International Journal of Innovative Research in Computer and Communication Engineering
印刷版ISSN：2320-9798
电子版ISSN：2320-9801
出版年度：2014
卷号：2
期号：11
出版社：S&S Publications
摘要：Fast addition plays an important role in advanced digital system. Recently, reconfigurable adders havebeen widely employed to achieve real time processing of media signals. This paper presents a design-forreconfigurability(DFR) technique for carry look ahead adders (CLAs)[1]. The various adder structures can be usedto execute addition such as serial and parallel structures and most of researches have done research on the designof high-speed, low-area, or low- power adders. Adders like ripple carry adder, carry select adder, Shannon adder,carry look ahead adder, carry skip adder, carry save adder [2] exist numerous adder implementations each withgood attributes and some drawbacks. This paper focuses on the implementation and simulation of 4-bit, 8-bit and 16-bit carry look-ahead adder based on Verilog code [3] and compared for their performance in Xilinx [1]. We haverecorded the performance improvements in propagating the carry and generating the sum when compared with thetraditional carry look ahead adder designed in the same technology [4] [5].
关键词：Carry-Look ahead Adder (CLA) Block; HDL Languages; Xilinx ISE Simulator.
