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  • 标题:Design of Low Power Low Voltage DCVS Logic Based Comparator
  • 本地全文:下载
  • 作者:K.Mathumathi ; P.D.Hemapriya
  • 期刊名称:International Journal of Innovative Research in Computer and Communication Engineering
  • 印刷版ISSN:2320-9798
  • 电子版ISSN:2320-9801
  • 出版年度:2014
  • 卷号:2
  • 期号:11
  • 出版社:S&S Publications
  • 摘要:In this paper comparator designed based on the DCVS (Differential Cascode Voltage Switch) logic. Thecomparator is a circuit that compares an analog signal with another analog signal or reference and outputs a binarysignal based on comparison. There are many logic styles used to design the comparator but here using DCVS logic.The DCVS logic has been the most widely used structure to design CMOS circuits and it produce both polarities ofoutput. The overall performance of the comparator is based on power consumption and speed. Compared to CMOS thislogic reduces the delay time and power dissipation of the comparator. In this paper to form the DCVS logic morenumber of switching transistors are added. Compared with the double tail comparator in the proposed comparator boththe power consumption and delay time are significantly reduced.
  • 关键词:DCVS logic; Low Power; Delay
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