期刊名称：International Journal of Innovative Research in Computer and Communication Engineering
印刷版ISSN：2320-9798
电子版ISSN：2320-9801
出版年度：2014
卷号：2
期号：11
出版社：S&S Publications
摘要：Multithreshold CMOS is very effective for reducing standby leakage power during long periods ofinactivity. Recently, a power-gating scheme to support multiple poweroff modes and reduce the leakage power duringshort periods of inactivity. This scheme is highly sensitive to process variations. Therefore,we propose a clock gatingtechnique that is tolerant to process variations and scalable to more than two intermediate power-off modes. The clockgating improves the design architecture and reduces the delay, area and power consumption. In addition, it can becombined with existing techniques to offer further static power reduction benefits. The analysis and simulation resultsdemonstrate the effectiveness of the proposed design.
关键词：Leakage power; clock gating; multi mode power switches; power consumption reduction;reconfigurable power-gating structure
