期刊名称：International Journal of Innovative Research in Computer and Communication Engineering
印刷版ISSN：2320-9798
电子版ISSN：2320-9801
出版年度：2014
卷号：2
期号：12
出版社：S&S Publications
摘要：The need for ultra low-power, area efficient, and high speed analog-to-digital converters is pushingtoward the use of dynamic regenerative comparators to maximize speed and power efficiency. In this paper, an analysison the delay of the dynamic comparators will be presented and analytical expressions are derived. From the analyticalexpressions, designers can obtain an intuition about the main contributors to the comparator delay and fully explore thetradeoffs in dynamic comparator design. Based on the presented analysis, a new dynamic comparator is proposed,where the circuit of a conventional double-tail comparator is modified for low-power and fast operation even in smallsupply voltages. Without complicating the design and by adding few transistors, the positive feedback during theregeneration is strengthened, which results in remarkably reduced delay time. It is shown that in the proposed dynamiccomparator both the power consumption and delay time are significantly reduced.
关键词：Double-tail comparator; dynamic clocked comparator; high-speed analog-to-digital converters;(ADCs);low-power analog design.
