期刊名称：International Journal of Innovative Research in Computer and Communication Engineering
印刷版ISSN：2320-9798
电子版ISSN：2320-9801
出版年度：2015
卷号：3
期号：2
DOI：10.15680/ijircce.2015.0302098
出版社：S&S Publications
摘要：In this paper we focus on the design of I2C bus controller and the interface between the two integrateddevices i.e. microcontroller and EEPROM, the microcontroller like as a master controller and, the EEPROM like asslave for serial communication in embedded system. The I2C Interface is operating in 7-bit address mode. We can sayone master is able to manage 27 or 128 slaves. The components of the I2C bus controller is consist of only abidirectional two wire and standard protocol which communicate between two integrated circuit or device. First one isserial data (SDA) line and second is serial clock (SCL) line. The I2C protocol was given by Philips Semiconductors forfaster devices to communicate with slower devices and each other without data loss. The complete module of I2C buscontroller is designed in VHDL and simulated in ModelSIM. The design is also synthesized in Xilinx XST 14.1.
