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  • 标题:Energy Efficient Design for Full Adder Logic Implementation
  • 本地全文:下载
  • 作者:Rakhi Saha ; Sambita Dalal ; Satyasis Mishra
  • 期刊名称:International Journal of Innovative Research in Computer and Communication Engineering
  • 印刷版ISSN:2320-9798
  • 电子版ISSN:2320-9801
  • 出版年度:2015
  • 卷号:3
  • 期号:3
  • DOI:10.15680/ijircce.2015.0303098
  • 出版社:S&S Publications
  • 摘要:In VLSI applications, area, delay and power are the important factors which must be taken into accountwhich can be minimized by using Reversible logic design. The reversible logic gates are now finding profound as wellas promising applications in emerging growing paradigms such as Quantum computing, Quantum Dot CellularAutomata, Optical Computing, Digital Signal Processing, Nanotechnology and etc. This paper presents the noveldesigns of full adder by using improved reversible logic gates. The main purpose of designing using reversible circuitis to decrease the number of garbage outputs and the number of gates and transistor used.
  • 关键词:Reversible logic; Garbage output; Full adder; Logic gates
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