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  • 标题:Design and Implementation of 2by3 Prescaler using Different Logic in CMOS 45nm Technology
  • 本地全文:下载
  • 作者:Siddharth A. Koshiyar ; Narendra J. Patadiya ; Prof. Bharat H. Nagpara
  • 期刊名称:International Journal of Innovative Research in Computer and Communication Engineering
  • 印刷版ISSN:2320-9798
  • 电子版ISSN:2320-9801
  • 出版年度:2015
  • 卷号:3
  • 期号:3
  • DOI:10.15680/ijircce.2015.0303190
  • 出版社:S&S Publications
  • 摘要:Frequency division is one of the important applications of flip-flops. A wide-band frequency synthesizerimplemented by phase-locked loop (PLL) uses prescaler (also called N/N+1 counter) as fundamental block. In PLLhigh frequency output of VCO is coupled directly to the prescaler directly. As process technology is reducing, channellength and supply voltage is decreasing rapidly. Therefore prescaler has to work at high frequency as well as lowoperating voltage. Using pass transistor or CMOS Technology are the incorporation of additional logic gates betweenthe flip-flops to achieve the two different division ratios, the speed of the prescaler is affected by creating anotherpropagation delay and the increases the switching power.
  • 关键词:LT-Spice-IV; VCO (voltage controlled oscillator); DMP (Dual Modulus Prescaler) TG (transmission;gate);PTL(pass transistor logic).
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