期刊名称：International Journal of Innovative Research in Computer and Communication Engineering
印刷版ISSN：2320-9798
电子版ISSN：2320-9801
出版年度：2015
卷号：3
期号：4
DOI：10.15680/ijircce.2015.0304070
出版社：S&S Publications
摘要：The usage of the low power consumptions devices in today’s global village has become pervasive andindispensable in almost every walk of life. The thrust is towards reducing the high power energy consumption, requiredto reduce cost of the circuitry, while increasing the speed of performances in any operations. A high speed low powerconsumption positive edge triggered Delayed (D) flip-flop can be design for increasing the speed of counter in Phaselocked loop, using 32 nm CMOS technology. Here we design D flip-flop for Phase locked loop (PLL). Phase lockedloop is an important analog circuit used in various communication applications such as frequency synthesizer, radiocomputer, clock generation microprocessors etc. The design counter can be used in the divider chip of the phase lockedloop. A divide counter is required in the feedback loop to increase the VCO frequency above the input referencefrequency. The propose circuit will faster than conventional circuit as it will have fast reset operation. The circuit willconsumes less power as it prevents short circuit power consumption. The circuit operates at low voltage power supply.The CMOS based fast D flip-flop circuit can be design and simulated by using Microwind 3.1 tool.
关键词：Phase Locked Loop (PLL); D flip-flop; Phase Frequency Detector (PFD) and Voltage Control;Oscillator (VCO).
