期刊名称：International Journal of Innovative Research in Computer and Communication Engineering
印刷版ISSN：2320-9798
电子版ISSN：2320-9801
出版年度：2015
卷号：3
期号：4
DOI：10.15680/ijircce.2015.0304151
出版社：S&S Publications
摘要：Phase locked loop is a familiar circuit for high frequency application and very short interlocking time. Inthis paper we have implemented and analysed All Digital Phase locked loop (ADPLL), as the present applicationsrequires a low cost, low power and high speed Phase locked loops. The design is synthesized in Xilinx ISE software.The pure digital phase locked loop is attractive because it is less sensitive to noise and operating conditions than itsanalog counterpart. This project gives details of the basic blocks of an ADPLL. In this project it is been planned toimplementation of ADPLL. Its simulation results are verified for all the corners of inputs. The ADPLL is planned for200 MHz central frequency.
