期刊名称：International Journal of Innovative Research in Computer and Communication Engineering
印刷版ISSN：2320-9798
电子版ISSN：2320-9801
出版年度：2015
卷号：3
期号：5
DOI：10.15680/ijircce.2015.0305022
出版社：S&S Publications
摘要：In this paper Design of high speed MAC unit based on Vedic multiplier algorithm. Generally MACuseful application such as Digital signal processing like FFT transform , Convolution and correlation. MAC ishardware based module therefore first design of multiplier block and second one is adder block. in this paper toimplementation 64bit MAC with reduce the delay and increase the speed of system. The coding done by verilog-HDLand its synthesis and simulation on XILINX ISE.14.5 tool.
