期刊名称：International Journal of Innovative Research in Computer and Communication Engineering
印刷版ISSN：2320-9798
电子版ISSN：2320-9801
出版年度：2015
卷号：3
期号：6
DOI：10.15680/ijircce.2015.0306005
出版社：S&S Publications
摘要：In electronics, adder is an obligatory component of every single integrated circuit. Adder is primary fastand secondly consumed less power and also chip area. We define various adders to perform addition method in VLSItechnology. Full adder designing with respect to low power is becoming more popular now adays. It is an essentialcomponents of every ALU block. To perform fast arithmetic operations, ripple carry adder is one of the fastest addersused in many data- processing processors. In this paper we analysed a full adder circuit in different sub-microntechnologies and obtain low power and minimum delay of it. We also design area efficient layout of full adderschematic. With the help of full adder low power with delay consumed model we design a ripple carry adder schematicand make an area efficient layout of it[1].
关键词：Low power model; minimum delay; ripple carry adder; Sub- micron technologies and layout
