期刊名称：International Journal of Innovative Research in Computer and Communication Engineering
印刷版ISSN：2320-9798
电子版ISSN：2320-9801
出版年度：2015
卷号：3
期号：6
DOI：10.15680/ijircce.2015.0306112
出版社：S&S Publications
摘要：ASIC Implementation of I2C Master bus controller has been proposed in this paper. I2C is one the mostdominant protocol for on chip communication between different modules. The FPGA implementation of I2C mastercontroller contains many features to incorporate vast varieties of applications and I2C standard; hence it’s bulky, slowwith high power requirement. While, all features of generic design are rarely used fully in any particular IC. Hence, amodified design with fewer features but withhigh power efficiency, less delay and less area requirement, has beenproposed in this paper. This design is best suitable for any ASIC design where for on-chip communication, a serial businterface is required. Moreover, Proposed I2C Master Controller has been designed for ASIC, which makes the designhighly portable on any SOC chip as well. The entire custom ASIC implementation of proposed design has been done inCadence Tool chain with 45nm technology standard library. A thorough comparison has been done between FPGAimplementation of I2C Controller and the ASIC implementation of the proposed design.
关键词：I2C Master controller; Serial protocol; ASIC implementation; Custom ASIC design;Serial;communication.
